1. Field of the Invention
This invention relates to P-N junction isolation grids for semiconductor devices and method of making the same.
2. Description of the Prior Art
W. G. Pfann describes in "Zone Melting", John Wiley and Sons, Inc. New York (1966), a thermal gradient zone melting process to produce P-N junctions within the bulk of a semiconductor. In his method, either sheets or wires of a suitable metallic liquid are moved through a semiconductor material in a thermal gradient. Doped liquid-epitaxial material is left behind as the liquid wire migration progresses. However, several investigators found the planar liquid zone was unstable and droplets of liquid broke away from the zone and were trapped in the recrystallized material. Thus, material produced by TGZM was not suitable for the manufacture of semiconductor devices. No real success was ever achieved in any of these efforts to the best of our knowledge and no commercially feasible adaptation of TGZM exists elsewhere today. Earlier efforts used relatively thick liquid zones because of the ease in placing a metal foil in between two semiconductor crystals. Problems of wetting and instability of the zone were recognized but no solution was found. In addition, observation of the crystal produced showed trapped liquid and unstable migration.
In our copending applications:
High Velocity Thermomigration Method of Making Deep Diodes, Ser. No. 411,015 now U.S. Pat. No. 3,898,106; Deep Diode Device and Method, Ser. No. 411,009 now U.S. Pat. No. 3,902,925; Deep Diode Device and Method, Ser. No. 411,001, now abandoned in favor of Ser. No. 552,154; Method of making Deep Diode Devices, Ser. No. 411,150 now U.S. Pat. No. 3,901,736; High Velocity Thermal Migration Process of Making Deep Diodes, Ser. No. 411,021, now U.S. Pat. No. 3,910,801; and Stabilized Droplet Migration Method of Making Deep Diodes Having Uniform Electrical Properties, Ser. No. 411,008 now U.S. Pat. No. 3,899,361; assigned to the same assignee of this application, we teach the stability of droplets, planar zones and line migrations and critical dimensions affecting the migration thereof. However, we have found that even with this available knowledge the formation of a P-N junction isolation grid is not a simple adaptation of the available knowledge we had developed.
Therefore, it is an object of this invention to provide a new and improved method of manufacturing a P-N junction isolation grid for semiconductor devices.
Another object of this invention is to provide a new and improved method for manufacturing a P-N isolation grid for semiconductor devices which correlates planar orientation of the surface of the semiconductor materials, directions of wires as disposed on the surface and the direction of the migration of the wires relative to the crystallography of the semiconductor material.
Other objects of this invention will, in part, be obvious and will, in part, appear hereinafter.